The present invention relates to a graphic display apparatus with a vector generating circuit.
As a vector generating system in the graphic display apparatus, the Bresenham system is been well known. It is described in detail in an article "Algorithm for Computer Control of a Digital Plotter" by J. E. Bresenham, IBM Syst. J4(1), 25-30, 1965. Therefore, it is briefly explained here.
As shown in FIG. 2, when a start point P.sub.s and an end point P.sub.E of a vector are given, q.sub.m and q.sub.n are compared in order to select one of points P.sub.i and P.sub.j to be displayed next to P.sub.s. The selected one is closer to a straight line to be displayed. In an example of the vector shown in FIG. 2, ##EQU1## where .DELTA.X is a distance in X-direction and .DELTA.Y is a distance in Y-direction. An initial value R.sub.o in a discrimination R is defined by the following, EQU R.sub.o =.DELTA.X*(q.sub.m -q.sub.n)=2*.DELTA.Y-.DELTA.X (4)
When R.sub.o .gtoreq.0, P.sub.j is selected, and when R.sub.o &lt;0, P.sub.i is selected. When one of points P.sub.i+1 and P.sub.j+1 is selected, the next value R.sub.1 for the discrimination is given by the following, EQU R.sub.1 =.DELTA.X*(q.sub.m+1 -q.sub.n+1)=R.sub.0 +2*(.DELTA.Y-.DELTA.X)(5)
if P.sub.j was selected previously, and EQU R.sub.1 =.DELTA.X*(q.sub.m+1 -q.sub.n+1)=R.sub.0 +2*.DELTA.Y(6)
if P.sub.i was selected previously. Depending on which one of P.sub.j and P.sub.i was selected previously, that is, on a sign of the previous discrimination R.sub.0, an increment 2*(.DELTA.X-.DELTA.Y) or 2*.DELTA.Y is added to the discrimination R.sub.0 in order to obtain the next discrimination R.sub.1. In the illustrated example, all of .DELTA.X, .DELTA.Y and .DELTA.X-.DELTA.Y are positive or zero. Depending on the combination of the signs of .DELTA.X, .DELTA.Y and .DELTA.X-.DELTA.Y, the value of the discrimination R differs from that described above and the address is determined by incrementing or decrementing. Many prior art pattern processing apparatus generate the vectors by the Bresenham system but they take a long time to generate the vectors because the addresses are generated by microprograms.
The vector generation method is briefly explained below. FIG. 1 shows a graphic display apparatus previously considered and attempted by the present inventors but not known in public. Numerals 101-103 denote registers for storing an initial value R, a positive increment P and a negative increment N, respectively, numeral 108 denotes an arithmetic logic unit (ALU), numeral 109 denotes a circuit for generating an address of a microinstruction, numeral 110 denotes a control storage for storing the microinstruction, numeral 111 denotes a microinstruction decode circuit, numeral 112 denotes a register for holding an X-direction end address X.sub.E of a vector, numeral 113 denotes a register for holding a Y-direction end address Y.sub.E, numeral 114 denotes a counter for holding an X-direction write address X.sub.s, numeral 115 denotes a register for holding a Y-direction write address Y.sub.s, numerals 116 and 117 denote compare circuits, numeral 118 denotes an AND gate, numeral 119 denotes a refresh memory for storing information of each picture cell at each position corresponding to the picture cell on a display device (not shown), numeral 120 denotes a write timing signal generating circuit for the refresh memory 119, numeral 121 denotes an AND gate, and numeral 122 denotes a write data forming circuit for the refresh memory 119. The method for generating the vector in the above graphic display apparatus is now explained in connection with an example in which a vector from a point (X.sub.o, Y.sub.o) to a point (X.sub.3, Y.sub.2) shown in FIG. 2 is generated. Based on the Bresenham algorithm, the initial value R of the discrimination, the positive increment P and the negative increment N are calculated by the following formulas. EQU R=2*.DELTA.Y-.DELTA.X (1) EQU P=2*(.DELTA.Y-.DELTA.X) (2) EQU N=2*.DELTA.Y (3)
where .DELTA.Y is a Y-direction component (Y.sub.E -Y.sub.s) of the vector, and .DELTA.X is an X-direction component (X.sub.E -X.sub.s). In the example shown in FIG. 2, .DELTA.Y=2 and .DELTA.X=3, and R, P and N are 1, -2 and 4, respectively. It is now assumed that R, P and N are set in the registers 101-103 of FIG. 1, the start point (X.sub.0, Y.sub.0) is set in the counters 114 and 115 and the end point (X.sub.3, Y.sub.2) are set in the registers 112 and 113. FIG. 3 shows only a portion of vector generating microprogram stored in the control storage 110 of FIG. 1. Referring to the microprogram of FIG. 3, when a microinstruction 301 is fetched from the control storage 110, a control line 144 for designating the writing to the refresh memory 119 is enabled by the decoder 111. The signal on the control line 144 is ANDed with an output timing signal 135 from the timing signal generator 120 by the AND gate 121 to produce a write pulse 133 to the refresh memory 119. The outputs of the counters 114 and 115 are supplied to the refresh memory 119 as addresses. In the present example, a dot is generated at the position (X.sub.0, Y.sub.0) shown in FIG. 2. The data to be written into the refresh memory 119 is determined by an output signal 136 from the data generator 122. When the refresh memory 119 comprises a plurality of planes each corresponding to one color, the data may be a plurality of bits each corresponding to one color. In the present example, however, for the sake of simplicity, the colors are ignored and it is assumed that the refresh memory 119 comprises one plane which stores only intensity data. It is assumed that the data line 136 always carries a logical "1" signal. When a microinstruction 302 is next fetched from the control storage 110, the microinstruction address generating circuit 109 generates an address of a microinstruction 303 if the conditioning signal 134 is valid, and generates an address of a microinstruction 308 if the signal 134 is invalid. The conditioning signal 134 is an AND function of the signals 137 and 138 and the compare circuit 116 renders the signal 134 valid when the contents of the registers 112 and 114 are equal, and the compare circuit 117 renders the signal 138 valid when the contents of the registers 113 and 115 are equal. In the present example, the conditioning signal 134 is valid when the address reaches the point (X.sub.3, Y.sub.2). Accordingly, when the address is at the point (X.sub.0, Y.sub.0), the microinstruction address generating circuit 109 generates the address of the microinstruction 303 as the next microinstruction address. When the microinstruction 303 is fetched, the control line 140 is enabled by the decoder 111. The control line 140 causes the counter 114 to count up. The microinstruction 304 is next fetched and the microinstruction address generating circuit 109 generates the address of the microinstruction 305 as the address of the microinstruction to be next fetched if the conditioning signal 139 is valid, and generates the address of the microinstruction 307 if the conditioning signal 139 is invalid. The conditioning signal is rendered valid by the ALU 108 when the content of the register 101 is positive. In the present example, the content R is 1 and the microinstruction 305 is next fetched. The microinstruction 305 renders the control line 142 valid, which causes the counter 115 to count up. When the microinstruction 306 is next fetched, the contents of the registers 101 and 102 are added in the ALU 108 to produce a sum and the sum is stored in the register 101 through a bus 130. A control signal therefor is similar to a control signal in a conventional microprogram controlled system and hence it is omitted in FIG. 1. The microinstruction 307 is executed when the conditioning signal 139 is invalid. It instructs to add the contents of the registers 101 and 103 and store a sum in the register 101. After the execution of the microinstruction 306 or 307, the address generating circuit 109 is controlled to fetch the microinstruction 301. The above microinstructions are executed until the conditioning signal 134 becomes valid. As a result, dots are generated at points (X.sub.0, Y.sub.0), (X.sub.1, Y.sub.1), (X.sub.2, Y.sub.1) and (X.sub.3, Y.sub.2) shown in FIG. 2, so that a vector is generated.
In the vector generation method, in the graphic display apparatus described above, five to six microinstructions are needed to generate one dot, the vector cannot be generated at a high speed.